1. Field of the Invention
The invention relates to system-on-chip (SoC) arrangements and, in particular, to reconfigurable integrated circuits (ICs).
2. Description of the Related Art
The inherent limits of sub-micrometric technology pose new challenges to the world of reconfigurable platforms. The capability of shrinking into silicon very large quantities of transistors permits integration in a single die of very complex functions and features. At the same time, the complexity of last-generation reconfigurable devices is not fully met by the sophistication of the tools used to map applications on these architectures. Users of reconfigurable device platforms must devote significant efforts in “extracting” the maximum expected potential performance levels through “custom” mapping solutions.
Meanwhile, “Do-It-All Devices” are now being considered in order to execute very complex software applications with high performance/energy ratios required. Exemplary of these efforts are, e.g., the papers by N. Tredennick and B. Shimamoto: “You Want One Do-It-All Device. Special Report”, IEEE Spectrum, December 2003 or D. Verkest: “Machine Chameleon”, IEEE Spectrum, December 2003.
A large number of works in the literature deal with the advantages and disadvantages of coarse and fine grain computational resources; see, for instance:                Jonathan Rose, Abbas El Gamal and Alberto Sangiovanni-Vincentelli: “Architecture of Field-Programmable Gate Arrays”, Proceedings of the IEEE. Vol. 81, No. 7, July 1993;        Jack L. Kouloheris, Abbas El Gamal: “FPGA Performance versus Cell Granularity”, Custom Integrated Circuits Conference, 1991, Proceedings of the 1991 IEEE Custom Integrated Circuits Conference, pp. 6.2/1-6.2/4        J. Rose, R.J. Francis, D. Lewis and P. Chow: “Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency”, IEEE Journal Of Solid-State Circuits, Vol. 25, No. 5, October 1990, pp. 1217-1225; or        Satwant Singh, Jonathan Rose, Paul Chow, David Lewis: “The Effect of Logic Block Architecture on FPGA Performance”, IEEE Journal Of Solid-State Circuits, Vol. 27, No. 3, March 1992, pp. 281-287.        
Usually these papers primarily focus on FPGA (Field Programmable Gate-Array) basic blocks by trying to understand for instance, for a given application class, what is the right Look-Up Table (LUT) size or if it is preferable to have arrays of complex logic blocks like Arithmetical Logical Units (ALUs), and so on.
More recent works such as, e.g.:                Ken Eguro, Scott Hauck: “Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development”, Proceedings of the 11th Annual IEEE Symposium of Field-Programmable Custom Computing Machines (FCCM'03); or        Anthony L. Slade, Brent E. Nelson and Brad L. Hutchings:            “Reconfigurable Computing Application Frameworks”, Proceedings of the 11th Annual IEEE Symposium of Field-Programmable Custom Computing Machines (FCCM'03)
are based on the common idea that the present scenario for the reconfigurable platforms is more complex, so that a change in the abstraction level is required.
When analyzing a modern DSP application like an MPEG decoder, it becomes immediately clear that the high number of complex computational kernels makes it difficult to say what the right computational granularity could be. Present commercial solutions attempt to cope with the increasing demand for computational power by using hardware solutions involving the fastest available floating point/fixed point DSP devices (still writing down all the software in optimized assembler code) and state-of-the-art microprocessors. Marketing and energy considerations aside, both solutions are obviously able to give to the consumer world the required MIPS/FLOPS.
More to the point, if no specific requirements in terms of, e.g., cost, power consumption, integration, development times are to be complied with, the possibility exists of finding a hardware or software or combination hardware and software platform adapted to support the necessary computational load. For instance, a complex application such as a MPEG4 decoder can be managed by a dedicated SoC, a certain numbers of DSPs or a microprocessor having a sufficiently high clock frequency.
However, a reconfigurable device would offer the advantage of adapting itself in the most effective/efficient way to a specific application within a wide class of applications. The same remarks made in the foregoing generally apply to the prior art arrangements disclosed in patent documents such as, e.g., US-A-2004/0049672, US-A-2004/0143724, now U.S. Pat. No. 7,502,915, US-A-2003/0212853 or US-A-2003/0154357, now U.S. Pat. No. 7,325,123, and specifically, EP-A-1 443 417. This last-cited document discloses a reconfigurable system exemplary of this technology.